VIA APOLLO VP3 CHIPSET
|| VT82C597 north bridge controller chip
VT82C586B south bridge controller chip
(not actual size)
(not actual size)
- PC-97 compatible using VT82C586B South Bridge with ACPI Power Management
- Includes UltraDMA-33 EIDE, USB, and Keyboard/PS2-Mouse Interfaces plus RTC/CMOS on chip
- Single chip implementation for 64-bit Socket-7 CPU, 64-bit system memory, 32-bit PCI and 32-bit AGP interfaces
- 3.3V and sub-3.3V interface to CPU
- 3.3V (5V tolerant) DRAM, AGP,and PCI interface
- AGP v1.0 compliant
- PCI buses are synchronous to host CPU bus
- 33 MHz operation on the primary PCI bus
- 66 MHz PCI operation on the AGP bus
- Concurrent CPU and AGP access
- Flexible CPU Interface with support for Pentium®, and Pentium®, processor with MMX(tm), Cyrix 6x86(tm) and M2, and AMD K5 and K6 MMX(tm)
- Built-in nand-tree pin scan test capability
- 0.5um, high speed and low power CMOS process
Tyan Trinity ATX S1592S
|The Apollo VP3 is a high performance, cost effective, and energy efficient chip set for the implementation of AGP, PCI, and ISA in desktop and notebook personal computer systems based on 64-bit Socket-7 including; Intel Pentium® and Pentium® processor with MMXTM technology, AMD K5TM and K6TM, and Cyrix/IBM 6x86TM and 6x86MXTM super-scalar processors.
The Apollo-VP3 chip set consists of the VT82C597 system controller (456 pin BGA) and the VT82C586B PCI to ISA bridge (208
pin PQFP). The VT82C597 system controller provides superior performance between the CPU, optional synchronous cache,
DRAM, AGP bus, and PCI bus with pipelined, burst, and concurrent operation. For pipelined burst synchronous SRAMs, 3-1-1-1-
1-1-1-1 timing can be achieved for both read and write transactions at 66 MHz. Four cache lines (16 quadwords) of CPU/cache to
DRAM write buffers with concurrent write-back capability are included on chip to speed up cache read and write miss cycles.
The VT82C597 supports six banks of DRAMs up to 1GB. The DRAM controller supports standard Fast Page Mode (FPM)
DRAM, EDO-DRAM, Synchronous DRAM (SDRAM), and SDRAM-II with Double Data Rate (DDR) in a flexible mix / match
manner. The Synchronous DRAM interface allows zero wait state bursting between the DRAM and the data buffers at 66Mhz.
The six banks of DRAM can be composed of an arbitrary mixture of 1M / 2M / 4M / 8M / 16MxN DRAMs. The DRAM
controller also supports optional ECC (single-bit error correction and multi-bit detection) or EC (error checking) capability
separately selectable on a bank-by-bank basis.
The VT82C597 also supports full AGP v1.0 capability for maximum bus utilization including 2x mode transfers, SBA (SideBand
Addressing), Flush/Fence commands, and pipelined grants. An eight level request queue plus a four level post-write request queue
with thirty-two and sixteen quadwords of read and write data FIFO's respectively are included for deep pipelined and split AGP
transactions. A single-level GART TLB with 16 full associative entries and flexible CPU/AGP/PCI remapping control is also
provided for operation under protected mode operating environments.
The VT82C597 supports two 32-bit 3.3 / 5V system buses (one AGP and one PCI) with 64-bit to 32-bit data conversion. The
82C597 also contains a built-in bus-to-bus bridge to allow simultaneous concurrent operations on each bus. Five levels
(doublewords) of post write buffers are included to allow for concurrent CPU and PCI operation. Consecutive CPU addresses are
converted into burst PCI cycles with byte merging capability for optimal CPU to PCI throughput. For PCI master operation, forty-eight
levels (doublewords) of post write buffers and sixteen levels (doublewords) of prefetch buffers are included for concurrent
PCI bus and DRAM/cache accesses. The chipset also supports enhanced PCI bus commands such as Memory-Read-Line,
Memory-Read-Multiple and Memory-Write-Invalid commands to minimize snoop overhead. In addition, the chipset supports
advanced features such as snoop ahead, snoop filtering, L1 write-back forward to PCI master and L1 write-back merged with PCI
post write buffers to minimize PCI master read latency and DRAM utilization. The VT82C586B PCI to ISA bridge supports four
levels (doublewords) of line buffers, type F DMA transfers and delay transaction to allow efficient PCI bus utilization and (PCI-2.1
compliant). The VT82C586B also includes an integrated keyboard controller with PS2 mouse support, integrated DS12885 style
real time clock with extended 256 byte CMOS RAM, integrated master mode enhanced IDE controller with full scatter and gather
capability and extension to UltraDMA-33 / ATA-33 for 33MB/sec transfer rate, integrated USB interface with root hub and two
function ports with built-in physical layer transceivers, Distributed DMA support, and OnNow / ACPI compliant advanced
configuration and power management interface. A complete main board can be implemented with only six TTLs.
The Apollo VP3 chipset is ideal for high performance, high quality, high energy efficient and high integration desktop and
notebook AGP / PCI / ISA computer systems.
©-1997 VIA Technologies Inc.